In a NAND flash memory of the type widely available on the memory market, a tunnel insulating film for performing programming/erasing operations serves also as a gate insulating film that determines transistor characteristics of a cell. Thus, performance deterioration resulting from repeated programming/erasing operations causes a big problem. Such a reliability problem of the insulating film is disclosed, for example, in “Fujio Masuoka (chief editor) “Handbook of Flash Memory Technology”, On Demand Publishing, August 1993”.
Moreover, the NAND flash memory cannot be randomly written and thus is not suitable for recording a large quantity of data at high speed. Therefore, a large-capacity buffer memory is needed for recording dynamic images in real time.
A floating gate type using a floating gate for holding electric charges and a local trap type using a charge storage layer comprised of local traps contained in a nitride film or the like in a high proportion are mainly known as memory cell structures of the NAND flash memory. However, whether both types are suitable for finer structures of generations of 30 nm or later is uncertain, as given in the following points.
First, the floating gate type currently widely used commercially has, as a serious problem obstructing finer structures, an interference effect (inter-cell interference) between two mutually adjacent floating gates.
The inter-cell interference is disclosed, for example, by Andrea Ghetti, Luca Bortesi and Loris Vendrame, in “3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories”, Solid-State Electronics, vol. 49, Issue 11, November 2005, Pages 1805-1812.
The quickest and simplest method of solving this problem is to make thinner both a tunnel insulating film filling up a space between a channel and a floating gate and an inter-electrode insulating film (for example, IPD (Inter-Polysilicon Dielectric)) filling up a space between the floating gate and a control gate to implement shrinkage in a longitudinal direction simultaneously with shrinkage in a cross direction.
This is a method conforming to the scaling law (see, for example, R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE J. of SSC, vol. 9, no. 5, pp. 256-268, 1974) and is the most effective one. However, since programming/erasing operations need to be performed through a tunnel insulating film, charge traps occur on the floating gate side while performing programming operations and charge traps occur on the substrate side while performing erase operations.
Therefore, with an increasing number of times of programming/erasing operations to/from a memory cell, a difference (threshold window) between a threshold in a programming state and that in an erasing state becomes smaller.
Thus, when tackling the problem of reliability of a tunnel insulating film, a problem specific to non-volatile memories, making a tunnel insulating film thinner is difficult to realize. Therefore, making a NAND flash memory of the floating gate type finer results in distorted scaling in which only shrinkage in the cross direction is implemented. This reveals the problem caused by an inter-cell interference effect.
The local trap type, on the other hand, has structurally no inter-cell interference and, in addition, leak phenomena of a tunnel insulating film are limited to local traps related to a leak path that arises in the tunnel insulating film. Thus, the local trap type is also superior in leak resistance (see, for example, SONY CX-PAL, issue 52, Device that traveled in outer space, Non-volatile memory device technology for low-cost combined mounting “MONOS”).
From these points described above, local trap type memory cells are expected to be a prospective successor after processes to make floating gate type memory cells finer come to an end.
Since the local trap type has a thin tunnel insulating film, there is an advantage that charge traps are less likely to occur in the tunnel insulating film due to lower energy of tunnel electrons than that of the floating gate type.
However, if programming/erasing operations are performed repeatedly in the local trap type, a charge trap in the tunnel insulating film occurs, as in the floating gate type. Such a trap naturally reveals a problem of reliability of the tunnel insulating film.
In addition, if processes of making the local trap type finer are advanced, the number of local traps in the charge storage layer decreases, revealing a fundamental weak point that the amount of charges that can be stored decreases. For this reason, even a slight amount of charge that slips out from a local trap in a charge storage layer in a finer memory cell has an enormous effect on the threshold of the memory cell.
If, for example, the trap density of a charge storage layer is 1×1012 cm−2, the number of traps of the charge storage layer for a control gate whose plane size is 20 nm×20 nm, will be just four. If only one of the four traps becomes a leak path, 25% of the total charge will be lost.
Such fluctuations in the number of local traps render memory cell operations unstable.
That is, if such fluctuations in the number of local traps are further considered when the number of local traps (number of electrons held) in the charge storage layer decreases and a threshold swing between a programming state and an erasing state of a memory cell becomes smaller. Read operation can not execute, when no threshold window or a narrow threshold window generates.
Under such circumstances, a next-generation memory called a quantum dot memory is proposed.
The quantum dot memory can roughly be divided into two types.
One is a technology that utilizes many quantum dots having fluctuations as an aggregate, considering the fact that position control and quality maintenance of single quantum dots are difficult.
For example, quantum dots are embedded in a tunnel insulating film to improve programming characteristics. This technology is disclosed, for example, by R. Ohba, N. Sugiyama, J. Koga, and S. Fujita, in “Silicon nitride memory with double tunnel junction”, 2003 Symposium on VLSI Technology Dig. Tech. Paper.” Moreover, quantum dots themselves may be used in place of local traps.
These technologies may partially improve conventional memory cell characteristics, but since quantum dots are embedded corresponding to one floating gate, the floating gate itself cannot be made so microscopic that quantum dot properties appear, thus fundamental progress is not expected. In addition, manufacturing costs increase because reliability of a tunnel insulating film containing a quantum dot layer becomes lower than that of a tunnel insulating film of the floating gate type due to the presence of quantum dots.
The other is a technology that utilizes quantum dots as a floating gate.
A floating gate of 10 nm is self-aligningly formed in a trough of a recess without position fluctuations on a longitudinal structure in which a tetrahedral shaped recess is cut out in a GaAs substrate (see, for example, M. Shima, Y. Sakuma, T. Futatsugi, Y. Awano, and N. Yokoyama, “Tetrahedral shaped recess channel HEMT with a floating quantum dot gate”, IEDM Tech. Dig., pp. 437-440, December 1998).
Since data is stored depending on whether or not one electron is present, for example, terabit-level scaling can be handled. However, the size of a recess opening is actually several micrometers and thus, a cell occupied area will be vastly larger than a file memory using a silicon substrate.
That is, the key to making a cell finer is to make an opening finer. Making a recess opening finer is limited also by limitations of making a GaAs substrate thinner because a source and a drain are arranged vertically. In addition, the GaAs substrate is originally not appropriate for a file memory because of increased bit costs.
From what has been described above, realization of a new memory architecture is desired that uses a silicon technology, solves a problem of reliability by separating a gate insulating film and a tunnel insulating film, operates even on a scale where a floating gate behaves like quantum dots, and further is randomly programmable.